• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Digital photomultiplier of OR combination of pulses. The photomultiplier comprises a set of macrocells, each one comprising at least two microcells (1), each one being connected to an output node (7) following an OR scheme and achieves great energy efficiency by deactivating each of the microcells. (1) when these are activated practically simultaneously, and that would have been otherwise masked by the OR scheme. For this, each of the microcells comprises an active extinguishing and recharging circuit (2), an avalanche diode (8), a first deactivation transistor (45) with its gate connected to an external processor (5), and its drain and source associated with the active extinguishing and recharging circuit (2), a second deactivation transistor (46) with its gate connected to an external processor (5), and its source associated with the active extinguishing and recharging circuit (2). (Machine-translation by Google Translate, not legally binding)
    公开号:ES2849224A1
    申请号:ES202030127
    申请日:2020-02-14
    公开日:2021-08-16
    发明作者:Ion Vornicu；Galan Ricardo Carmona；Vazquez Angel Rodriguez
    申请人:Consejo Superior de Investigaciones Cientificas CSIC；Universidad de Sevilla；
    IPC主号:
    专利说明:

    [0003] OBJECT OF THE INVENTION
    [0005] The object of the invention is a digital photomultiplier with a series of microcells each comprising an active quenching and recharge circuit (AQR, Active Quenching and Recharge) with a variable Dead Time , and combined following an OR scheme. A great efficiency in the use of energy is obtained by deactivating each of the individual microcells of the rest of the microcells when these are activated practically simultaneously, since they would have been otherwise masked by the OR scheme.
    [0007] BACKGROUND OF THE INVENTION
    [0009] Silicon photomultipliers (SiPM, Silicon Photo-Multiplier) consist of arrays of single-photon event-sensitive avalanche diodes (SPAD ) that share, in the most basic scheme, an output node. Each SPAD accompanied by its extinction resistance constitutes a microcell. The avalanche currents generated in the microcells aggregate in a common node, obtaining a current that constitutes the output of the photomultiplier.
    [0011] The main problem with this analog SiPM scheme is that the avalanche currents develop at their maximum amplitude and can reach a very considerable magnitude. This represents too high a power consumption for some applications.
    [0013] In addition to this, the quenching resistor is designed in such a way that with little current a pulse is produced at the voltage sufficient to pull the diode out of the breakdown voltage. The problem with this is that the diode recharges through the same resistance, which, because it is so high, leads to long recharging times. This means that the device will be rendered useless to capture a new photon for an excessively long period, a dead time. This phenomenon of accumulation ( pile-up) of photons leads to an error in the resolution with which the pulse energy is measured and in the determination of the time of flight.
    [0015] Since the information provided by each SPAD is binary, that is, from the existence of an avalanche the detection of a photon is deduced, regardless of the magnitude of the avalanche current, letting the avalanche evolve is an unnecessary energy waste.
    [0017] Digital silicon photomultipliers (d-SiPM) solve this by incorporating a microcell monostable that generates a pulse of limited duration associated with the onset of each avalanche. This monostable is part of an active extinguishing and recharging circuit. Since the magnitude of the avalanche does not report additional information, the active extinguishing circuit stops the avalanche very soon, reducing power consumption, and accelerates the recharge of the diode until an acceptable dead time is achieved, and generally adjustable, with the consequent reduction of accumulation ( pile-up ).
    [0019] The pulses generated by the microcells are conducted towards the same node, to count and time them, in order to obtain estimates of the number of photons detected and the flight time, respectively. To combine the pulses that come from different microcells, an OR tree is usually used, which adds all the pulses except those that are less than the new dead time delimited by the duration of the monostable pulses.
    [0021] The main problem with this d-SiPM scheme is the reduction of the Fill Factor (FF), which implies a loss of sensitivity. This reduction is due, on the one hand, to the fact that the active extinguishing and recharging circuit occupies a larger area than the extinguishing resistance, which means that the FF of the microcell decreases and, consequently, that of the SiPM itself.
    [0023] On the other hand, pulse counting and timing circuits, time-to-digital converters (TDC: Time-to-Digital Converters) also occupy an area that would otherwise be destined to detect photons. The number of counters and TDCs is the result of a compromise between spatial and temporal resolution. If we had as many as microcells, reducing the sensitive area might be unacceptable. If we reduce the number of counters and TDCs, we generate accumulation again ( pile-up) with the consequent loss of photons.
    [0024] An example of the state of the art would be document W02013018006A1, which describes a photon detector that includes a SPAD array with circuitry to determine the position of the SPADs that have made a detection.
    [0026] This device comprises elements configured to store the position coordinates within the matrix of those SPADs that have been fired. In order to determine the row to which the SPAD that has been triggered belongs, all the SPADs belonging to the same row share an OR gate that combines the outputs. In the same way, all SPADs that belong to the same column share an OR gate that allows determining the column in which the SPAD that has been triggered is located.
    [0028] On the other hand, document US2006202129A1 describes an integrated circuit with a matrix of microcells, each one composed of a SPAD, a buffer to shape the digital output pulse and several transistors that act as a driver for a column bus connected well to a TDC or an asynchronous digital meter. The possibility of decoupling the pixel reading circuit by means of a transformer is also considered.
    [0030] In US2017242136A1 a photomultiplier semiconductor device (SPM) is shown. The SPM comprises a set of photosensitive elements, connected to a first electrode arranged to provide a bias voltage to these photosensitive elements.
    [0032] It also comprises a set of resistive elements for extinguishing the avalanche, each associated with a corresponding photosensitive element. These resistive elements are connected at the other end to a second electrode arranged as a polarization electrode. Coupled to each of the nodes that join a photosensitive element with a resistive element, we have a capacitive load in parallel with another resistive load and eventually a diode, which are all connected to a common third electrode to provide an output signal from the device.
    [0034] DESCRIPTION OF THE INVENTION
    [0036] One aspect of the described d-SiPM architecture that has not been considered above is the unnecessary power consumption introduced by avalanches that occur within the dead time. These avalanches will generate a pulse that will not go beyond the OR combination and will therefore not be counted. Our proposal consists of associating N microcells in a macrocell in which the photodiodes are deactivated during the dead time that occurs after the triggering of an avalanche in one of the diodes of the same.
    [0037] The invention being described is therefore a digital photomultiplier based on macrocells containing: N avalanche photodiodes, an active circuit for extinguishing the avalanche and recharging for each diode, very compact and of low consumption, with shared monostable that gives rise to an adjustable dead time, and a mechanism for combining the pulses generated by the SPADs that make up the macrocell that reduces power consumption.
    [0039] This macrocell is compatible with detection schemes in digital silicon photomultipliers in which an OR-combination of the pulses is performed. The key to energy efficiency lies in the fact that the triggering of an avalanche in one of the SPADs prevents the rest of the SPADs in the macrocell from firing.
    [0041] This aspect is important when designing large digital photomultipliers, since we need each microcell to have a minimum consumption and a minimum noise level. It is convenient, under these conditions, to take into account the limitations of OR pulse combination techniques.
    [0043] In combination-OR schemes, a whole series of cells with avalanche diodes sensitive to a single photon converge on the same channel, so that their outputs are combined in an OR logic. Each of these cells comprises a single photon event sensitive avalanche diode and a quench and recharge circuit that can be active or passive.
    [0045] In the case of using a passive extinguishing and recharging circuit, high energy consumption occurs since the amplitude of the pulses and the width of the pulses are controlled with the same element, this is not convenient to achieve a high pulse compression .
    [0047] Furthermore, in this type of OR-combination scheme, when several detections occur in several of the avalanche diodes simultaneously, it is not possible to differentiate in the common output in which of the diodes the detection has occurred. Furthermore, this overlapping of detections tends to occur between diodes that are adjacent, that is, that belong to the same macrocell. Therefore diodes with overlapping sensing are consuming power unnecessarily.
    [0049] In a conventional OR-combination scheme, the avalanches that are generated in adjacent cells almost at the same time as the first one, are masked by the pulse combination system, thus producing useless energy consumption, since these avalanches would not provide additional information. This unnecessary consumption can be critical when designing photomultipliers with a large number of sensing elements.
    [0051] In order to respond to these problems, the present invention has been developed, which consists of a digital photomultiplier of combination-OR of pulses that is formed by macrocells. Each of these macrocells comprises at least two microcells, each of the microcells being connected to an output node following an OR scheme. The grouping of microcells allows the reduction of the quenching and recharging circuitry through the sharing of some transistors, which results in an improvement of the FF.
    [0053] Each of the microcells comprises an Active Quenching and Recharge (AQR) circuit block. Each of the blocks is made up of a series of transistors, the arrangement of which will be explained later, and is associated with a point through which a signal can be introduced that starts the active recharge.
    [0055] In each of the microcells, a single photon event-sensitive avalanche diode is also positioned, with its anode connected to the active extinguishing and recharging circuit, a first deactivation transistor with its gate connected to an external processor, and its drain and source associated with the active extinguishing and recharging circuit, and a second deactivation transistor with its gate connected to an external processor, its drain associated with the output node and its source associated with the active extinguishing and recharging circuit.
    [0057] This assembly may further comprise a high clamp transistor with its drain connected to the common node.
    [0059] As indicated, the active extinguishing and recharging circuit comprises, in a preferred embodiment of the invention, four transistors. A first transistor with its gate connected to the source of the second deactivation transistor, its drain connected to the anode of the avalanche diode and its source connected to a common node to the microcells, a second transistor with its gate connected to the source of the second transistor of deactivation, its drain connected to the drain of the first deactivation transistor and its source connected to an activation signal input, a third transistor with its gate connected to the point through which the active recharge start signal is received, its drain connected to the source of the first deactivation transistor and its source connected to the common node between microcells, and a fourth transistor with its gate connected to the drain of the first transistor of deactivation, its drain connected to the source of the second activation transistor and its source connected to ground.
    [0061] Each macrocell of the photomultiplier object of the invention may additionally comprise a monostable for generating the active recharge start signal connected to the active recharge circuit.
    [0063] The exposed digital photomultiplier macrocell has a number of strengths:
    [0064] - compactness: it is achieved by sharing the control electronics, that is, the connection to a single external processor, among all the microcells of the same macrocell, thus achieving a 30% filling factor (FF, Filling Factor). The active extinguishing and recharging circuit of each avalanche diode is implemented by four transistors. Compared to a microcell containing a passive quenching and recharging circuit, the proposed quenching and recharging block represents only a 13% fill factor penalty, which can be compensated for by using micro-lenses, - energy efficiency : The proposed macrocell benefits from an inherent limitation to pulse OR-combining by deactivating the microcells in each macrocell when there is an overlap of pulses.
    [0066] DESCRIPTION OF THE DRAWINGS
    [0068] To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, according to a preferred example of a practical embodiment thereof, a set of drawings is attached as an integral part of said description. where, with an illustrative and non-limiting nature, the following has been represented:
    [0070] Figure 1.- Shows a schematic view of a macrocell of the digital photomultiplier for the OR combination of pulses in an embodiment with four microcells.
    [0072] Figure 2.- Shows a schematic view of the monostable.
    [0074] PREFERRED EMBODIMENT OF THE INVENTION
    [0076] A preferred embodiment of the present invention is described below with the aid of Figures 1 and 2.
    [0077] Figure 1 shows a diagram of a macrocell of the digital combination OR pulse photomultiplier object of the invention, which in this embodiment comprises microcells (1), specifically four. Each of the microcells (1) is connected to an output node (7), following an OR scheme.
    [0079] Each of the microcells (1) comprises an active extinguishing and recharging circuit (2). In turn, each of these active extinguishing and recharging circuits (2) comprises four transistors (3).
    [0081] Furthermore, each of the microcells (1) comprises a point through which it receives the signal to start the active recharge (6) associated with each active extinguishing and recharging circuit (2).
    [0083] Each of the microcells (1) also has an avalanche diode (8) sensitive to single photon events or SPAD ( Single Photon Avalanche Diode), with its anode connected to the active extinguishing and recharging circuit (2).
    [0085] Finally, each of the microcells (1) comprises a first deactivation transistor (45) with its gate connected to an external processor (5), its drain connected to the drain of the second transistor (32) and its source connected to the drain of the third transistor (33), and a second deactivation transistor (46) with its gate connected to an external processor (5), its drain associated with the output node (7) and its source connected to the drain of the fourth transistor (34).
    [0087] Both the first deactivation transistor (45) and the second deactivation transistor (46) are intended to deactivate the microcell (1) in which they are comprised, so that the microcells (1) can be deactivated completely individually. other
    [0089] As indicated, the gates of the deactivation transistors (45, 46) are connected to an external processor (5), specifically to SRAM ( Single Random Access Memory) memories. This is necessary to be able to turn off the noisy avalanche diodes (8) when operating in normal mode or to measure intercommunication or cross-talk between microcells (1) when the circuit is being characterized.
    [0090] However, in those technologies that have a sufficiently low Dark Count Rafe (DCR) per unit area, disable transistors (45, 46) are not required.
    [0092] All the microcells (1) are connected to an outlet node (7). Furthermore, an output node (7) is located between the drains of two of the second deactivation transistors (46). A high level setting transistor (12) is connected to this output node (7) by its drain.
    [0094] The transistors (3) of each of the microcells (1) are connected as described below. The first transistor (31) has its gate connected to the source of the second deactivation transistor (46), its drain connected to the anode of the avalanche diode (8) and its source connected to a junction node between microcells (9). The second transistor (32) has its gate connected to the source of the second turn-off transistor (46), its drain connected to the drain of the first turn-off transistor (45), and its source connected to a turn-on signal input.
    [0096] The third transistor (33) has its gate connected to the activation point of the active recharge (6), its drain connected to the source of the first deactivation transistor (45) and its source connected to the junction node between microcells (9), and the fourth transistor (34) with its gate connected to the drain of the first turn-off transistor (45), its drain connected to the source of the second turn-on transistor (46) and its source connected to ground.
    [0098] Although four microcells (1) are shown in this embodiment, the present invention enables a multi-microcell architecture (1) to be developed.
    [0100] The active recharge start signal is introduced into the active recharge activation point (6) through a monostable (11), the embodiment of which is shown in detail in figure 2. The monostable (11) has a time dead or variable DT (Dead Time ), so that an optimal value of the output pulse width is found, so that the correlated noise has a minimum value. Once the optimum value has been determined, the areas of a variable resistor (13) and an MOS capacitor (14) included in the monostable (11) can be optimized.
    [0102] The operation of the macrocell of the digital photomultiplier object of the present invention is now explained. We assume that all microcells are enabled (1) through the external processor (5), and that a pulse has been introduced as an active recharge signal at the active recharge activation point (6). As a consequence, all the avalanche diodes (8) are recharged bringing the voltage of their anodes to ground, through the third transistor (33) and the first deactivation transistor (45).
    [0104] This turns off the fourth transistor (34) in each of the microcells (1), allowing the output node (7) to be driven to a drive voltage VDD through the high clamp transistor (12). As a consequence, the second transistors (32) turn off and the first transistors (31) turn on, which keeps the anodes of the avalanche diodes (8) connected to ground and ready to be fired.
    [0106] Furthermore, if the activation voltage VDD is reached at the output node, then at the activation point of active recharge (6) the voltage is reduced, turning off the third transistors (33). Finally, the MOS capacitor (14) of the monostable (11) discharges.
    [0108] Next, we suppose that the avalanche diode (8) of the microcell (1) in the upper left corner of figure 1 is activated, by either a spurious or a true detection, which causes it to start to increase the voltage in its anode. Consequently, the fourth transistor (34) of this microcell (1) turns on and begins to reduce the voltage at the output node (7) through the second deactivation transistor (46). Before, the voltage at the output node (7) was only maintained by the second deactivation transistor (46).
    [0110] Furthermore, the second transistor (32) turns on, increasing the voltage at the anode of the single photon avalanche diode (8) even faster. This occurs with the activation of a positive feedback loop between the second transistor (32) and the fourth transistor (34).
    [0112] Reducing the voltage at the output node (7) turns off the first transistor (31). When the voltage at the anode of the single photon avalanche diode (8) reaches the activation voltage VDD, the avalanche diode (8) turns off, and will remain in this state until an active recharge start signal arrives at via the active recharge trigger point
    [0113] ( 6 ).
    [0115] It is now analyzed what happens in the rest of the microcells (1). The first detection caused by the single photon avalanche diode (8) of the upper left microcell (1) causes a negative transition of the voltage at the output node (7). As a consequence, the second transistor (32) and the fourth transistor (34) disable the first transistor (31) in each of the rest of the microcells (1), putting the voltage at the anode of the avalanche diodes (8) at the activation voltage VDD and deactivating the avalanche diodes (8). These will remain in this state until the arrival of a new signal through the active recharge activation node (6).
    [0117] Now analyzing figure 2, the negative transition of the voltage at the output node (7) activates a charge path through the variable resistor (13) of the monostable (11). The MOS capacitor (14) begins to charge with the time constant set by the delay time.
    [0119] When the voltage in the MOS capacitor (14) reaches a certain value, then the activation point of the active recharge (6) is activated, turning on all the third transistors (33) of each of the microcells (1).
    [0121] Then, all the voltages at the anodes of the single photon avalanche diodes (8) become zero, the fourth transistors (34) turn off, the voltage at the output node (7) is activated only through the high clamp transistor (12) that turns off the second transistors (32) and turns on the first transistors (31) recharging all single photon avalanche diodes.
    [0123] When the voltage at the output node (7) reaches the activation voltage VDD, the MOS capacitor (14) discharges rapidly, turning off the active recharge signal at the active recharge trigger point (6).
    [0125] At this point all the microcells (1) are armed, waiting for a detection that can activate any of them. If more than one microcell (1) is activated at the same time, the macrocell of the photomultiplier behaves similarly to how it has been explained, so that the rest of the microcells (1) are disabled as previously explained.
    [0127] In summary, any microcell (1) that is activated by a first detection automatically disables the rest of the microcells (1).
    [0129] This scheme allows energy savings so that the rest of the detections that occur after a first detection will be masked with the OR combination scheme between all the microcells (1).
    [0130] Finally, the deactivation mechanism of each individual microcell (1) will be exposed. We assume that the active recharge signal introduced by the active recharge activation point (6) of the microcell positioned in the upper left corner of figure 1 is zero, which turns off the first deactivation transistor (45) and the second deactivation transistor (46). This uncouples said microcell (1) from the output node (7) of the macrocell of the photomultiplier.
    [0132] If the avalanche diode (8) of said microcell (1) had been recharged before being deactivated, then it is ready to be activated once more, after remaining off while the active recharge signal is at zero. This occurs thanks to the second transistor (32) and fourth transistor (34) paired, which block the active recharge signal to zero.
    [0134] This makes it possible to deactivate each of the microcells (1) that would constitute a macrocell, using only one NMOS transistor, without requiring any additional PMOS transistor to raise the anode of the avalanche diode (8) to the activation voltage VDD.
    [0136] If a PMOS transistor had been used, as in other embodiments of the state of the art, it should have been connected between the anode of the avalanche diode (8) and the activation voltage VDD, its gate being controlled by the active recharge signal . This represents a significant improvement in the filling factor (FF, Filling Factor)
    权利要求:
    Claims (4)
    [1]
    1. - OR combination digital photomultiplier of pulses, characterized in that it comprises at least one macrocell, each of which comprises at least two microcells (1), each of the microcells (1) being connected to an output node ( 7) following an OR scheme and comprising each of the microcells (1):
    - an active extinguishing and recharging circuit (2),
    - an active recharge activation point (6) associated with the active extinguishing and recharging circuit (2),
    - an avalanche diode (8) sensitive to a single photon, with its anode connected to the active extinguishing and recharging circuit (2),
    - a first deactivation transistor (45) with its gate connected to an external processor (5), and its drain and source associated with the active extinguishing and recharging circuit
    ( 2 ),
    - a second deactivation transistor (46) with its gate connected to an external processor (5), its drain connected to the output node (7) and its source associated with the active extinguishing and recharging circuit (2).
    [2]
    2. - The photomultiplier of claim 1, wherein the at least one macrocell additionally comprises a high-level clamping transistor (12) with its drain connected to the output node (7).
    [3]
    3. - The photomultiplier of claim 1, wherein the active extinguishing and recharging circuit (2) comprises:
    - a first transistor (31) with its gate connected to the source of the second deactivation transistor (46), its drain connected to the anode of the avalanche diode (8) and its source connected to a junction node between microcells (9),
    - a second transistor (32) with its gate connected to the source of the second deactivation transistor (46), its drain connected to the drain of the first deactivation transistor (45) and its source connected to an activation voltage,
    - a third transistor (33) with its gate connected to the active recharge activation point (6), its drain connected to the source of the first deactivation transistor (45) and its source connected to the junction node between microcells (9), and
    - a fourth transistor (34) with its gate connected to the drain of the transistors (31, 32), its drain connected to the source of the second activation transistor (46) and its source connected to ground.
    [4]
    4. The photomultiplier of claim 1, wherein the at least one macrocell additionally comprises a monostable (11) for generating an active recharge signal connected to the activation point of the active recharge (6).
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    同族专利:
    公开号 | 公开日
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    WO2021160916A1|2021-08-19|
    引用文献:
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    CN106338339A|2016-10-17|2017-01-18|东南大学|Compact quenching detection circuit applied to array type single-photon avalanche diode |
    CN107222694A|2017-04-24|2017-09-29|深圳大学|A kind of single photon cmos image sensor image element circuit of low pixel size|
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    PCT/ES2021/070098| WO2021160916A1|2020-02-14|2021-02-11|Or pulse combination digital photomultiplier|
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